1. Technical Field
The present application relates generally to semiconductor devices and includes memory devices with temperature compensation.
2. Related Art
FIG. 1 is a schematic diagram of a flash memory cell 100. In simple terms, a flash memory cell includes an N-channel transistor 102 with an electrically isolated polysilicon floating gate 104 and a control gate 106. The flash memory cell 100 can be thought of as a capacitor which is charged and discharged.
The flash memory cell 100 is programmed by applying a high drain-to-source bias voltage with a high control gate voltage. Programming a flash memory cell 100 means that electrons are added to the floating gate 104. Adding electrons, or charge, to the floating gate 104 increases the flash memory cell's threshold voltage VT.
The flash memory cell 100 is erased (the charges are removed from the floating gate 104) by applying electrical voltages between the floating gate and the source or between the floating gate and the channel. After electrons are removed from the floating gate 104, the cell threshold voltage VT is reduced.
During a read operation, flash memory devices use precise charge sensing algorithms to determine whether a desired cell voltage has been achieved. A sense amplifier compares a cell's drain current with the drain current of a reference cell to determine whether the cell is programmed or erased. With multilevel cells (MLCs), comparisons between a cell and a reference cell are made to determine the different charge levels, or states, of the MLC. A method of controlling exactly how much charge is transferred to the floating gate of the MLC is used to ensure that enough charge to achieve a certain MLC state without overshooting that state. Further, a precise way to sense the cell voltage is used to determine the different MLC states.
With MLC flash memory, the data write may occur at one temperature, and the data read may occur at a different temperature. A flash cell's drain current is a function of the temperature conditions, and the precision of both writing and reading the MLC states may be affected. To minimize the affect on read/write precision, one solution may be to include reference cells on-chip, allowing cells and the reference cells to be affected similarly by temperature and power supply. However, for efficiency and space reasons, it may not be desirable to have reference cells on-chip.
Thus, it is desirable to find new approaches for improving precision of sensing or reading MLC states, particularly so as to minimize the affect of temperature variations on reading and sensing MLC states.